Friday, 23. June 2017

KTH Research Project Database

KTH Research Projec...

Architectural and Civil Engineering

Chemistry and biotechnology

Computer Science & Information Technology

Electrical Engineering


Physics and Energy

Production and Mechanical Engineering

Social Sciences and Humanities

Environment and sustainable development


»Research Fields

»Organisational Structure


Silicon Nanoelectronics Programme, NEMO (»Add to Infobox)

Research Leader: Docent Per-Erik Hellström
B. Gunnar Malm, Professor Mikael Östling

Integrated Devices and Circuits

After several years of continuous work to establish our nanofabrication platform with key process modules, we have now been able to take some major steps forward; these achievements are summarised as follows.

1) Nanowire definition and fabrication. We have refined our process for NW fabrication based on Sidewall Transfer Lithography (STL) in order to control the line edge roughness (LER) below 2 nm. We have further improved the STL process and fabricated 10-nm wide SiNWs with a line width roughness (LWR) below 1 nm, as shown in Fig. 1.

2) Tuning of the effective Schottky barrier height (SBH). We have developed two complementary processes SADS and SIDS for dopant segregation at the interface between silicide and Si aiming at modification of effective SBHs for NiSi and PtSi. Here, SADS stands for Silicide As Diffusion Source and SIDS Silicidation Induced Dopant Segregation. The dopants studied were P, As, B or In. Both processes have been found to yield an effective SBH down to about 0.1 eV for both Φbn (SBH for electrons) and Φbp (SBH for holes) according to measurement data on n- and p-type Schottky diodes. The reduction of SBHs is vital for efficient injection of carriers into the channel and is achievable for both NiSi and PtSi, which are the most used metal silicides for the source/drain (S/D) contacts. Both processes are of low-temperature nature which is critical for fabrication of future nano CMOS devices.

3) Fabrication of MOSFET and FinFET with Schottky barrier source/drain, i.e., SB-MOSFET and SB-FinFET. We have succeeded in making use of the STL technology to fabricate SB-MOSFET as well as SB-FinFET on ultrathin body silicon-on-insulator (UTB-SOI) substrates. Both p- and n-channel FETs were fabricated. Dopant segregation was found to be effective in improving the device performance for both SB-MOSFET and SB-FinFET. A representative double Fin-channel SB-FinFET is shown in Fig. 2, (a)-(c) for the physical features and (d) for the good switching performance.

Period: 2006-01-01 - 2008-03-31

Field-effect transistors, FinFET, Line edge roughness, Line width roughness, MOSFET, Schottky barrier height, Sidewall transfer litography
Show picture in detail
Figure 1. Topview of a SiNW fabricated by means of STL. The width of the NW is 10 nm with a one sigma LWR of 1 nm. The pictures were taken using a high-resolution scanning electron microscope.

Show picture in detail
Figure 2. (a) Top-view, obtained using a high-resolution scanning electron microscope, of a FinFET prepared using the STL process twice, first for the Fin-channel and second for the nano-gate. The source and drain contact leads are also visible. The scale bar is 400 nm. (b) Cross-sectional transmission electron microscopy (XTEM) micrographs of a Fin-channel, taken from a cut along the gate width. (c) XTEM micrograph of the nano-gate, taken from a cut along the Fin-channel. (d) Good performance of the FinFET with a large on/off of 106 and a decent on-current.


SSF (Swedish Foundation for Strategic Research)


»Advanced Search

INFOBOX (0/0) show all
Your infobox is empty

Powered by